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PIC12F519 Data Sheet
8-Pin, 8-Bit Flash Microcontrollers
*8-bit, 8-pin devices protected by Microchip's Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
(c) 2008 Microchip Technology Inc. DS41319B
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
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(c) 2008 Microchip Technology Inc.
PIC12F519
8-Pin, 8-Bit Flash Microcontroller
High-Performance RISC CPU:
* Only 33 Single-Word Instructions * All Single-Cycle Instructions except for Program Branches which are Two-Cycle * Two-Level Deep Hardware Stack * Direct, Indirect and Relative Addressing modes for Data and Instructions * Operating Speed: - DC - 8 MHz Oscillator - DC - 500 ns instruction cycle * On-chip Flash Program Memory - 1024 x 12 * General Purpose Registers (SRAM) - 41 x 8 * Flash Data Memory - 64 x 8
Low-Power Features/CMOS Technology:
* Standby Current: - 100 nA @ 2.0V, typical * Operating Current: - 11 A @ 32 kHz, 2.0V, typical - 175 A @ 4 MHz, 2.0V, typical * Watchdog Timer Current: - 1 A @ 2.0V, typical - 7 A @ 5.0V, typical * High Endurance Program and Flash Data Memory Cells - 100,000 write Program Memory endurance - 1,000,000 write Flash Data Memory endurance - Program and Flash Data retention: >40 years * Fully Static Design * Wide Operating Voltage Range: 2.0V to 5.5V - Wide temperature range - Industrial: -40C to +85C - Extended: -40C to +125C
Special Microcontroller Features:
* 8 MHz Precision Internal Oscillator - Factory calibrated to 1% * In-Circuit Serial ProgrammingTM (ICSPTM) * In-Circuit Debugging (ICD) Support * Power-on Reset (POR) * Device Reset Timer (DRT) * Watchdog Timer (WDT) with Dedicated On-Chip RC Oscillator for Reliable Operation * Programmable Code Protection * Multiplexed MCLR Input Pin * Internal Weak Pull-ups on I/O Pins * Power-Saving Sleep mode * Wake-up from Sleep on Pin Change * Selectable Oscillator Options: - INTRC: 4 MHz or 8 MHz precision Internal RC oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - LP: Power-saving, low-frequency crystal
Peripheral Features:
* 6 I/O Pins - 5 I/O pins with individual direction control - 1 input-only pin - High current sink/source for direct LED drive * 8-bit Real-Time Clock/Counter (TMR0) with 8-bit Programmable Prescaler.
(c) 2008 Microchip Technology Inc.
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PIC12F519
FIGURE 1: PIC12F519 8-PIN PDIP, SOIC, MSOP, 2X3 DFN DIAGRAM
PDIP, SOIC, MSOP
PIC12F519 VDD GP5/OSC1/CLKIN GP4/OSC2 GP3/MCLR/VPP 1 2 3 4 8 7 6 5 VSS GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI
DFN
GP5/OSC1/CLKIN GP4/OSC2 GP3/MCLR/VPP 2 3 4 PIC12F519 VDD 1 8 7 6 5 VSS GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI
Program Memory Device Flash (words) PIC12F519 1024
Data Memory I/O SRAM (bytes) 41 Flash (bytes) 64 6 1 Timers 8-bit
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PIC12F519
Table of Contents
1.0 General Description .................................................................................................................................................................. 5 2.0 PIC12F519 Device Varieties .................................................................................................................................................... 7 3.0 Architectural Overview .............................................................................................................................................................. 9 4.0 Memory Organization ............................................................................................................................................................. 13 5.0 Flash Data Memory ................................................................................................................................................................ 21 6.0 I/O Port ................................................................................................................................................................................... 23 7.0 Timer0 Module and TMR0 Register ........................................................................................................................................ 31 8.0 Special Features Of The CPU ................................................................................................................................................ 37 9.0 Instruction Set Summary ........................................................................................................................................................ 49 10.0 Development Support ............................................................................................................................................................. 57 11.0 Electrical Characteristics ........................................................................................................................................................ 61 12.0 DC and AC Characteristics Graphs and Charts ..................................................................................................................... 73 13.0 Packaging Information ............................................................................................................................................................ 83 Index ................................................................................................................................................................................................... 89 The Microchip Web Site ...................................................................................................................................................................... 91 Customer Change Notification Service ............................................................................................................................................... 91 Customer Support ............................................................................................................................................................................... 91 Reader Response ............................................................................................................................................................................... 92 Product Identification System ............................................................................................................................................................. 93
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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(c) 2008 Microchip Technology Inc.
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PIC12F519
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(c) 2008 Microchip Technology Inc.
PIC12F519
1.0 GENERAL DESCRIPTION
1.1 Applications
The PIC12F519 device from Microchip Technology is low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/single-cycle instructions. All instructions are single cycle except for program branches, which take two cycles. The PIC12F519 device delivers performance an order of magnitude higher than their competitors in the same price category. The 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easy to remember instruction set reduces development time significantly. The PIC12F519 product is equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from including INTRC Internal Oscillator mode and the power-saving LP (Low-power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC12F519 device is available in the cost-effective Flash programmable version, which is suitable for production in any volume. The customer can take full advantage of Microchip's price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC12F519 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full featured programmer. All the tools are supported on PC and compatible machines. The PIC12F519 device fits in applications ranging from personal care appliances and security systems to lowpower remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC12F519 device very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and PLDs in larger systems and coprocessor applications).
TABLE 1-1:
Clock Memory
FEATURES AND MEMORY OF PIC12F519
PIC12F519 Maximum Frequency of Operation (MHz) Flash Program Memory SRAM Data Memory (bytes) Flash Data Memory (bytes) 8 1024 41 64 TMR0 Yes 5 1 Yes Yes 33 8-pin PDIP, SOIC, MSOP, 2X3 DFN
Peripherals Features
Timer Module(s) Wake-up from Sleep on Pin Change I/O Pins Input Pins Internal Pull-ups In-Circuit Serial ProgrammingTM Number of Instructions Packages
The PIC12F519 device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC12F519 device uses serial programming with data pin GP0 and clock pin GP1.
(c) 2008 Microchip Technology Inc.
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PIC12F519
2.0 PIC12F519 DEVICE VARIETIES
2.2
When placing orders, please use the PIC12F519 Product Identification System at the back of this data sheet to specify the correct part number. A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section.
Serialized Quick Turn ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.
2.1
Quick Turn Programming (QTP) Devices
Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
(c) 2008 Microchip Technology Inc.
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(c) 2008 Microchip Technology Inc.
PIC12F519
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC12F519 device can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12F519 device uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (500 ns @ 8 MHz, 1 s @ 4 MHz) except for program branches. Table 3-1 below lists memory supported by the PIC12F519 device. The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-2.
TABLE 3-1:
PIC12F519 MEMORY
Program Memory Data Memory SRAM (bytes) 41 Flash Data (bytes) 64
Device Flash (words) PIC12F519 1024
The PIC12F519 device can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F519 device has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of "special optimal situations" make programming with the PIC12F519 device simple, yet efficient. In addition, the learning curve is reduced significantly. The PIC12F519 device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.
(c) 2008 Microchip Technology Inc.
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PIC12F519
FIGURE 3-1: PIC12F519 ARCHITECTURAL BLOCK DIAGRAM
Flash Program Memory 1K x 12 Flash Data Memory 64x8 Program 12 Bus Instruction Reg Direct Addr 5 11 Program Counter Data Bus 8 GPI/O GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI GP3/MCLR/VPP GP4/OSC2 GP55/OSC1/CLKIN
Stack 1 Stack 2
RAM 41 x 8 File Registers RAM Addr 9 Indirect Addr Addr MUX 5-7
FSR Reg 8 3 Device Reset Timer Instruction Decode & Control OSC1/CLKIN OSC2 Timing Generation Internal RC OSC Power-on Reset Watchdog Timer ALU 8 W Reg STATUS Reg
MUX
MCLR VDD, VSS
Timer0
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PIC12F519
TABLE 3-2:
Name GP0/ICSPDAT GP1/ICSPCLK GP2/T0CKI GP3/MCLR/VPP
PIC12F519 PINOUT DESCRIPTION
Function GP0 ICSPDAT GP1 ICSPCLK GP2 T0CKI GP3 MCLR VPP Type I/O I/O I/O I I/O I I I I I/O O I/O I I P P Input Type Output Type TTL ST TTL ST TTL ST TTL ST High Voltage TTL -- TTL XTAL ST -- -- CMOS CMOS CMOS -- CMOS -- -- -- -- CMOS XTAL CMOS -- -- -- -- Description Bidirectional I/O port with weak pull-up ICSPTM mode Schmitt Trigger Bidirectional I/O port with weak pull-up ICSPTM mode Schmitt Trigger Bidirectional I/O port Timer0 clock input Standard TTL input with weak pull-up MCLR input (Weak pull-up always enabled in this mode) Test mode high voltage pin Bidirectional I/O port XTAL oscillator output pin Bidirectional I/O port XTAL oscillator input pin EXTRC Schmitt Trigger input Positive supply for logic and I/O pins Ground reference for logic and I/O pins
GP4/OSC2 GP5/OSC1/ CLKIN VDD VSS Legend:
GP4 OSC2 GP5 OSC1 CLKIN VDD VSS
I = Input, O = Output, I/O = Input/Output, P = Power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog Voltage
(c) 2008 Microchip Technology Inc.
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PIC12F519
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC PC Fetch INST (PC) Execute INST (PC - 1) PC + 1 PC + 2 Internal Phase Clock Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Fetch INST (PC + 1) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 1)
EXAMPLE 3-1:
1. MOVLW 03H 2. MOVWF GPIO 3. CALL 4. BSF SUB_1 GPIO, 1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed.
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PIC12F519
4.0 MEMORY ORGANIZATION
FIGURE 4-1: MEMORY MAP
PC<11:0> CALL, RETLW Stack Level 1 Stack Level 2 10
The PIC12F519 memory is organized into program memory and data memory (SRAM). The self-writable portion of the program memory called Flash data memory, is located at addresses 400h-43Fh. As the device has more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using STATUS register bit, PA0. For the PIC12F519, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).
Reset Vector(1) On-chip Program Memory User Memory Space
0000h
4.1
Program Memory Organization for the PIC12F519
The PIC12F519 device has an 11-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Only the first 1K x 12 (0000h-03FFh) are physically implemented (see Figure 4-1). Accessing a location above these boundaries will cause a wrap-around within the 1K x 12 space. The effective Reset vector is a 0000h (see Figure 4-1). Location 03FFh contains the internal clock oscillator calibration value. This value should never be overwritten.
512 Word
01FFh 0200h
On-chip Program Memory 1024 Word
Flash Data Memory Space
03FFh 0400h
Flash Data Memory
043Fh 0440h
7FFh Address 0000h becomes the effective Reset vector. Location 03FFh contains the MOVLW XX internal oscillator calibration value. Flash data memory is non-executable.
Note 1:
2:
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PIC12F519
4.2 Data Memory (SRAM and FSRs)
4.2.2 SPECIAL FUNCTION REGISTERS
Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The Special Function Registers include the TMR0 register, the Program Counter Low (PCL), the STATUS register, the I/O register (port) and the File Select Register (FSR). In addition, the EECON, EEDATA and EEADR registers provide for interface with the Flash data memory. The PIC12F519 register file is composed of 10 Special Function Registers and 41 General Purpose Registers. The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
4.2.1
GENERAL PURPOSE REGISTER FILE
The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register (FSR). See Section 4.8 "Indirect Data Addressing: INDF and FSR Registers".
FIGURE 4-2:
FSR<5> File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Fh 10h 0
REGISTER FILE MAP
1 INDF(1) EECON PCL STATUS FSR EEDATA EEADR
INDF(1) TMR0 PCL STATUS FSR OSCCAL GPIO
20h
General Purpose Registers
Address map back to addresses in Bank 0
2Fh
30h General Purpose Registers General Purpose Registers
1Fh Bank 0 Note 1: Not a physical register. Bank 1
3Fh
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PIC12F519
TABLE 4-1:
Addr N/A N/A 00h 01h 02h(1) 03h 04h 05h 06h 21h 25h 26h Name TRISGPIO OPTION INDF TMR0 PCL STATUS FSR OSCCAL GPIO EECON EEDATA EEADR
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 -- Bit 6 -- Bit 5 TRISGPIO5 Bit 4 TRISGPIO4 Bit 3 TRISGPIO3 Bit 2 TRISGPIO2 Bit 1 TRISGPIO1 Bit 0 TRISGPIO0 Value on Power-on Reset --11 1111 1111 1111 xxxx xxxx xxxx xxxx 1111 1111 PA0 CAL4 GP5 -- EEDATA5 EEADR5 TO CAL3 GP4 FREE EEDATA4 EEADR4 PD CAL2 GP3 WRERR EEDATA3 EEADR3 Z CAL1 GP2 WREN EEDATA2 EEADR2 DC CAL0 GP1 WR EEDATA1 EEADR1 C -- GP0 RD EEDATA0 EEADR0 0-01 1xxx 110x xxxx 1111 111--xx xxxx ---0 x000 xxxx xxxx --xx xxxx
Contains Control Bits to Configure Timer0 and Timer0/WDT Prescaler Uses Contents of FSR to Address Data Memory (not a physical register) Timer0 Module Register Low Order 8 bits of PC GPWUF CAL6 -- -- -- -- CAL5 -- -- -- Indirect Data Memory Address Pointer
EEDATA7 EEDATA6
Legend: Note 1:
x = unknown, u = unchanged, - = unimplemented, read as `0' (if applicable). Shaded cells = unimplemented or unused The upper byte of the Program Counter is not directly accessible. See Section 4.6 "Program Counter" for an explanation of how to access these bits.
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PIC12F519
4.3 STATUS register
This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 9.0 "Instruction Set Summary".
REGISTER 4-1:
R/W-0 GPWUF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STATUS: STATUS REGISTER
U-0 -- R/W-0 PA0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GPWUF: Wake-up From Sleep on Pin Change bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset Unimplemented: Read as `0' PA0: Program Page Preselect bit 1 = Page 1 (000h-1FFh) 0 = Page 0 (200h-3FFh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred
bit 6 bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC12F519
4.4 OPTION Register
The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits. Note: If the T0SC bit is set to `1', it will override the TRIS function on the T0CKI pin.
REGISTER 4-2:
W-1 GPWU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION: OPTION REGISTER
W-1 GPPU W-1 T0CS W-1 T0SE W-1 PSA W-1 PS2 W-1 PS1 W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
x = Bit is unknown `0' = Bit is cleared
GPWU: Enable Wake-up On Pin Change bit 1 = Disabled 0 = Enabled GPPU: Enable Weak Pull-ups bit 1 = Disabled 0 = Enabled T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
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PIC12F519
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to calibrate the 8 MHz internal oscillator macro. It contains 7 bits of calibration that uses a two's complement scheme for controlling the oscillator speed. See Register 4-3 for details.
REGISTER 4-3:
R/W-1 CAL6 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1
OSCCAL: OSCILLATOR CALIBRATION REGISTER
R/W-1 CAL5 R/W-1 CAL4 R/W-1 CAL3 R/W-1 CAL2 R/W-1 CAL1 R/W-1 CAL0 U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CAL<6:0>: Oscillator Calibration bits 0111111 = Maximum frequency * * * 0000001 0000000 = Center frequency 1111111 * * * 1000000 =Minimum frequency Unimplemented: Read as `0'
bit 0
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PIC12F519
4.6 Program Counter
4.6.1 EFFECTS OF RESET
As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits <8:0> of the PC are provided by the GOTO instruction word. The Program Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4-3). For a CALL instruction, or any instruction where the PCL is the destination, bits <7:0> of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-3). Instructions where the PCL is the destination, or modify PCL instructions, include MOVWF PCL, ADDWF PCL and BSF PCL,5. Note: Because PC<8> is cleared in the CALL instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code. The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is pre-selected. Therefore, upon a Reset, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.
4.7
Stack
The PIC12F519 device has a two-deep, 12-bit wide hardware PUSH/POP stack. A CALL instruction will PUSH the current value of Stack 1 into Stack 2 and then PUSH the current PC value, incremented by one, into Stack Level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored. A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into Stack Level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in Stack Level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Note 1: There are no Status bits to indicate stack overflows or stack underflow conditions. 2: There are no instruction mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions.
FIGURE 4-3:
LOADING OF PC BRANCH INSTRUCTIONS
0 PCL
GOTO Instruction 10 9 8 7 PC
Instruction Word PA0 7 Status CALL or Modify PCL Instruction 10 9 8 7 PC PCL Instruction Word Reset to `0' 0 Status 0 0
PA0 7
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PIC12F519
4.8 Indirect Data Addressing: INDF and FSR Registers
EXAMPLE 4-1: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF ;register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected). The FSR is an 8-bit wide register. It is used in conjunction with the INDF Register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. FSR<5> is used to select between banks (0 = Bank 0, 1 = Bank 1). FSR<7:6> are unimplemented and read as `11'.
NEXT
MOVLW MOVWF CLRF INCF BTFSC GOTO
CONTINUE : :
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 5 4 (FSR) 0
(FSR) 5
4
(opcode)
Bank Select
Location Select 0 00h 1
Bank
Location Select
Data Memory
0Fh 10h
1Fh Bank 0
3Fh Bank 1
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PIC12F519
5.0 FLASH DATA MEMORY CONTROL
4. Write the new byte of data and any saved bytes back to the appropriate addresses in Flash data memory.
The Flash data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFRs).
To prevent accidental corruption of the Flash Data Memory, an unlock sequence is required to initiate a write or erase cycle. This sequence requires that the bit set instructions used to configure the EECON register happen exactly as shown in Example 2 and Example 3, depending on the operation requested.
5.1
Reading Flash Data Memory
To read a Flash data memory location the user must: * Write the EEADR register * Set the RD bit of the EECON register The value written to the EEADR register determines which Flash data memory location is read. Setting the RD bit of the EECON register initiates the read. Data from the Flash data memory read is available in the EEDATA register immediately. The EEDATA register will hold this value until another read is initiated or it is modified by a write operation. Program execution is suspended while the read cycle is in progress. Execution will continue with the instruction following the one that sets the WR bit. See Example 1 for sample code.
5.2.1
ERASING FLASH DATA MEMORY
A row must be manually erased before writing new data. The following sequence must be performed for a single row erase. 1. 2. 3. 4. Load EEADR with an address in the row to be erased. Set the FREE bit to enable the erase. Set the WREN bit to enable write access to the array. Set the WR bit to initiate the erase cycle.
If the WREN bit is not set in the instruction cycle after the FREE bit is set, the FREE bit will be cleared in hardware. If the WR bit is not set in the instruction cycle after the WREN bit is set, the WREN bit will be cleared in hardware. Sample code that follows this procedure is included in Example 2. Program execution is suspended while the erase cycle is in progress. Execution will continue with the instruction following the one that sets the WR bit.
EXAMPLE 1:
BANKSEL EEADR
READING FROM FLASH DATA MEMORY
; ; ;Data Memory ;Address to read ; ;EE Read ;W = EEDATA
MOVF DATA_EE_ADDR, W MOVWF EEADR BANKSEL EECON1 BSF EECON, RD MOVF EEDATA, W
EXAMPLE 2:
BANKSEL EEADR
ERASING A FLASH DATA MEMORY ROW
; LOAD ADDRESS OF ROW TO ; ERASE ; ; SELECT ERASE ; ENABLE WRITES ; INITITATE ERASE
Note: Only a BSF command will work to enable the Flash data memory read documented in Example 1. No other sequence of commands will work, no exceptions.
MOVLW MOVWF BSF BSF BSF
EE_ADR_ERASE EEADR EECON,FREE EECON,WREN EECON,WR
5.2
Writing and Erasing Flash Data Memory
Flash data memory is erased one row at a time and written one byte at a time. The 64-byte array is made up of eight rows. A row contains eight sequential bytes. Row boundaries exist every eight bytes. Generally, the procedure to write a byte of data to Flash data memory is: 1. 2. Identify the row containing the address where the byte will be written. If there is other information in that row that must be saved, copy those bytes from Flash data memory to RAM. Perform a row erase of the row of interest.
Note 1: The FREE bit may be set by any command normally used by the core. However, the WREN and WR bits can only be set using a series of BSF commands, as documented in Example 1. No other sequence of commands will work, no exceptions. 2: Bits <5:3> of the EEADR register indicate which row is to be erased.
3.
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PIC12F519
5.2.2 WRITING TO FLASH DATA MEMORY EXAMPLE 4:
MOVF BSF XORWF BTFSS GOTO
WRITE VERIFY OF DATA EEPROM
;EEDATA has not changed ;from previous write ;Read the value written ; ;Is data the same ;No, handle error ;Yes, continue
Once a cell is erased, new data can be written. Program execution is suspended during the write cycle. The following sequence must be performed for a single byte write. 1. 2. 3. 4. Load EEADR with the address. Load EEDATA with the data to write. Set the WREN bit to enable write access to the array. Set the WR bit to initiate the erase cycle.
EEDATA, W EECON, RD EEDATA, W STATUS, Z WRITE_ERR
5.4
Code Protection
If the WR bit is not set in the instruction cycle after the WREN bit is set, the WREN bit will be cleared in hardware. Sample code that follows this procedure is included in Example 3.
Code protection does not prevent the CPU from performing read or write operations on the Flash data memory. Refer to the code protection chapter for more information.
EXAMPLE 3:
BANKSEL MOVLW MOVWF MOVLW MOVWF BSF BSF
WRITING A FLASH DATA MEMORY ROW
; ; ; ; ; ; LOAD ADDRESS LOAD DATA INTO EEDATA REGISTER ENABLE WRITES INITITATE ERASE
EEADR EE_ADR_WRITE EEADR EE_DATA_TO_WRITE EEDATA EECON,WREN EECON,WR
Note 1: Only a series of BSF commands will work to enable the memory write sequence documented in Example 2. No other sequence of commands will work, no exceptions. 2: For reads, erases and writes to the Flash data memory, there is no need to insert a NOP into the user code as is done on mid-range devices. The instruction immediately following the "BSF EECON,WR/RD" will be fetched and executed properly.
5.3
Write Verify
Depending on the application, good programming practice may dictate that data written to the Flash data memory be verified. Example 4 is an example of a write verify.
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PIC12F519
6.0 I/O PORT
6.2 TRIS Registers
As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin's Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. The Output Driver Control registers are loaded with the contents of the W Register by executing the TRIS f instruction. A `1' from a TRISGPIO Register bit puts the corresponding output driver in a high-impedance (Input) mode. A `0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The TRISGPIO register is "write-only". Bits <5:0> are set (output drivers disabled) upon Reset. Note: If the T0CS bit is set to `1', it will override the TRISGPIO function on the T0CKI pin.
6.1
GPIO
GPIO is an 8-bit I/O register. Only the low-order 6 bits are used (GP<5:0>). Bits 7 and 6 are unimplemented and read as `0's. Please note that GP3 is an input-only pin. The Configuration Word can set several I/O's to alternate functions. When acting as alternate functions, the pins will read as `0' during a port read. Pins GP0, GP1, and GP3 can be configured with weak pull-ups and also for wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If GP3/MCLR is configured as MCLR, weak pullup is always on and wake-up on change for this pin is not enabled.
TABLE 6-1:
Pin GP0 GP1 GP2 GP3 GP4 GP5 GP6
WEAK PULL-UP ENABLED PINS
WPU Y Y N Y(1) N N N WU Y Y N Y N N N
Note 1: When MCLRE = 1, the weak pull-up on GP3/MCLR is always enabled. 2: WPU = Weak pull-up; WU = Wake-up.
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PIC12F519
REGISTER 6-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GPIO: GPIO REGISTER
U-0 -- R/W-x GP5 R/W-x GP4 R/W-x GP3 R/W-x GP2 R/W-x GP1 R/W-x GP0 bit 0
Unimplemented: Read as `0' GP<5:0>: GPIO I/O Pin bits 1 = GPIO pin is >VIH min. 0 = GPIO pin is REGISTER 6-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
TRISGPIO: TRI-STATE GPIO REGISTER
U-0 -- W-1 TRISGPIO5 W-1 TRISGPIO4 W-1 TRISGPIO3 W-1 TRISGPIO2 W-1 TRISGPIO1 W-1 TRISGPIO0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' TRISGPIO<5:0>: GPIO Tri-State Control bits 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output
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PIC12F519
6.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in Figure 6-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF GPIO, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRISGPIO must be cleared (= 0). For use as an input, the corresponding TRISGPIO bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output.
FIGURE 6-1:
GPPU
PIC12F519 EQUIVALENT CIRCUIT FOR I/O PINS - GP0/GP1
VDD VDD
Data
D
Q I/O Pin
Data Latch WR CK Q
WREG
D
Q VSS
TRIS Latch TRIS `F' CK Q
RD Port Q D
Wake-up on change Latch CK
Pin Change
GP0/ICSPDAT * General purpose I/O * In-Circuit Serial ProgrammingTM data * Wake-up on input change trigger
GP1/ICSPCLK * General purpose I/O * In-circuit Serial ProgrammingTM clock * Wake-up on input change trigger
(c) 2008 Microchip Technology Inc.
DS41319B-page 25
PIC12F519
FIGURE 6-2: GP2/TOCK1
* General Purpose I/O * A Clock Input for Timer0
VDD
Data
D
Q I/O Pin
Data Latch WR CK Q
WREG
D
Q VSS
TRIS Latch TRIS `F' TOCS CK Q
RD Port
To Timer0
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PIC12F519
FIGURE 6-3: GP4/OSC2
* General Purpose I/O * A crystal resonator connection
VDD From OSC1 Oscillator Circuit
DATA BUS
D
Q I/O Pin
Data Latch WR PORT CK Q
WREG
D
Q VSS
TRIS Latch TRIS `F' CK Q
INTOSC RC
RD PORT
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DS41319B-page 27
PIC12F519
FIGURE 6-4: GP5/OSC1/CLKIN
VDD From OSC2 Oscillator Circuit
DATA BUS
D
Q I/O Pin
Data Latch WR PORT CK Q
WREG
D
Q VSS
TRIS Latch TRIS `F' CK Q
* General Purpose I/O * A crystal resonator connection * A clock input
RD PORT
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PIC12F519
FIGURE 6-5: GP3 (WITH WEAK PULLUP AND WAKE-UP ON CHANGE)
GPPU
MCLRE
Weak
Reset Input Pin(1)
VSS
Data Bus RD Port Q
Wake-up on change latch
D
CK
Pin Change
Note 1:
GP3/MCLR pin has a protection diode to VSS only.
TABLE 6-2:
Name
GPIO TRISGPIO STATUS OPTION
SUMMARY OF PORT REGISTERS
Bit 7
-- -- GPWUF GPWU
Bit 6
-- -- -- GPPU
Bit 5
GP5 PA0 T0CS
Bit 4
GP4 TO T0SE
Bit 3
GP3 PD PSA
Bit 2
GP2 Z PS2
Bit 1
GP1 DC PS1
Bit 0
GP0 C PS0
Value on POR
Value on all other Resets
--xx xxxx --uu uuuu
TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 --11 1111 --11 1111 0-01 1xxx q-0q quuu 1111 1111 1111 1111
Legend:
x = unknown, u = unchanged, - = unimplemented, read as `0', Shaded cells = unimplemented, read as `0', q = depends on the condition
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DS41319B-page 29
PIC12F519
6.4
6.4.1
I/O Programming Considerations
BIDIRECTIONAL I/O PORTS
EXAMPLE 6-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT
Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit 5 of GPIO will cause all eight bits of GPIO to be read into the CPU, bit 5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit 0 is switched into Output mode later on, the content of the data latch may now be unknown. Example 6-1 shows the effect of two sequential Read-Modify-Write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired OR", "wired AND"). The resulting high output currents may damage the chip.
;Initial GPIO Settings ;GPIO<5:3> Inputs ;GPIO<2:0> Outputs ; ; GPIO latch GPIO pins ; ------------------BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h; TRIS GPIO ;--10 -ppp --11 pppp ; Note 1: The user may have expected the pin values to be `--00 pppp'. The 2nd BCF caused GP5 to be latched as the pin value (High).
6.4.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 6-6). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
FIGURE 6-6:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 PC + 3 NOP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetched GP<5:0> Port pin written here Instruction Executed MOVWF GPIO (Write to GPIO) Port pin sampled here MOVF PORTB,W (Read PORTB) PC MOVWF GPIO PC + 1 MOVF GPIO, W PC + 2 NOP
This example shows a write to GPIO followed by a read from GPIO. Data setup time = (0.25 TCY - TPD) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic.
NOP
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PIC12F519
7.0 TIMER0 MODULE AND TMR0 REGISTER
Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.1 "Using Timer0 with an External Clock". The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit, PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 7.2 "Prescaler" details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 7-1. The Timer0 contained in the CPU core follows the standard baseline definition.
The Timer0 module has the following features: * * * * 8-bit timer/counter register, TMR0 Readable and writable 8-bit software programmable prescaler Internal or external clock select: - Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register.
FIGURE 7-1:
TIMER0 BLOCK DIAGRAM
Data Bus FOSC/4 0 1 1 PSout Sync with Internal Clocks 8 TMR0 Reg
T0CKI pin T0SE(1)
Programmable Prescaler(2) 3 PS2, PS1, PS0(1)
0
PSout (2 cycle delay) Sync
PSA(1)
T0CS
(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer.
FIGURE 7-2:
PC (Program Counter) Instruction Fetch Timer0 Instruction Executed T0
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC - 1 PC MOVWF TMR0 PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
T0 + 2
NT0
NT0 + 1
NT0 + 2
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
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DS41319B-page 31
PIC12F519
FIGURE 7-3:
PC (Program Counter) Instruction Fetch Timer0 Instruction Executed T0
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC - 1 PC MOVWF TMR0 PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 1
NT0
NT0 + 1
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
TABLE 7-1:
Add res s
01h N/A N/A
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset
xxxx xxxx PSA PS2 PS1 PS0 1111 1111
Name
TMR0 OPTION TRISGPIO
Value on All Other Resets
uuuu uuuu 1111 1111 --11 1111
Timer0 - 8-bit Real-Time Clock/Counter GPWU -- GPPU -- T0CS T0SE
TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 --11 1111
Legend:
x = unknown, u = unchanged, - = unimplemented, read as `0', Shaded cells = unimplemented, read as `0'
DS41319B-page 32
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PIC12F519
7.1 Using Timer0 with an External Clock
When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4 TOSC (and a small RC delay of 4 Tt0H) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of Tt0H. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.
7.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-4). Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 2 Tt0H) and low for at least 2 TOSC (and a small RC delay of 2 Tt0H). Refer to the electrical specification of the desired device.
7.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-4 shows the delay from the external clock edge to the timer incrementing.
FIGURE 7-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler Output (2) External Clock/Prescaler Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (1) (3)
T0 + 2
Note 1: 2: 3:
Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = 4 TOSC max. External clock if no prescaler selected; prescaler output otherwise. The arrows indicate the times at which sampling occurs.
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PIC12F519
7.2 Prescaler
EXAMPLE 7-1:
An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section 8.6 "Watchdog Timer (WDT)"). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice versa.
CHANGING PRESCALER (TIMER0 WDT)
CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and Prescaler MOVLW b`00xx1111' OPTION CLRWDT ;PS<2:0> are 000 or 001 MOVLW b`00xx1xxx' ;Set Postscaler to OPTION ;desired WDT rate
The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescaler contains all `0's.
To change the prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.
EXAMPLE 7-2:
CLRWDT MOVLW
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler b`xxxx0xxx' ;Select TMR0, new ;prescale value and ;clock source
7.2.1
SWITCHING PRESCALER ASSIGNMENT
OPTION
The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.
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PIC12F519
FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/ WDT PRESCALER(1)
Data Bus 0 T0CKI pin 1 M U X 1 M U X Sync 2 Cycles TMR0 Reg 8 TCY (= FOSC/4)
0 T0SE T0CS
PSA
0 M U X
8-bit Prescaler 8 8-to-1 MUX PS<2:0>
Watchdog Timer
1
PSA WDT Enable bit 0 MUX 1 PSA
WDT Time-Out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
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PIC12F519
NOTES:
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PIC12F519
8.0 SPECIAL FEATURES OF THE CPU
The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through a change-on-input-pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4 MHz or 8 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC12F519 microcontroller has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. These features are: * Oscillator Selection * Reset: - Power-on Reset (POR) - Device Reset Timer (DRT) - Wake-up from Sleep on Pin Change * Watchdog Timer (WDT) * Sleep * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM The PIC12F519 device has a Watchdog Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable. If using INTRC or EXTRC, the DRT provides a 1 ms (nominal) delay.
8.1
Configuration Bits
The PIC12F519 Configuration Words consist of 12 bits. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type; one bit is the Watchdog Timer enable bit, one bit is the MCLR enable bit and one bit is for code protection (Register 8-1).
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PIC12F519
REGISTER 8-1:
-- bit 7 bit 7 bit 6 Unimplemented: Read as `1' CPDF: Code Protection bit - Flash Data Memory 1 = Code protection off 0 = Code protection on IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC frequency 0 = 4 MHz INTOSC frequency MCLRE: Master Clear Enable bit 1 = GP3/MCLR pin functions as MCLR 0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD CP: Code Protection bit - User Program Memory 1 = Code protection off 0 = Code protection on WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<1:0>: Oscillator Selection bits 00 = LP oscillator with 18 ms DRT(2) 01 = XT oscillator with 18 ms DRT(2) 10 = INTOSC with 1 ms DRT(2) 11 = EXTRC with 1 ms DRT(2)
CONFIG: CONFIGURATION WORD REGISTER(1)
CPDF IOSCFS MCLRE CP WDTE FOSC1 FOSC0 bit 0
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1: Refer to the "PIC12F519 Memory Programming Specification", DS41316 to determine how to program/erase the Configuration Word. 2: DRT length (18 ms or 1 ms) is a function of clock mode selection. It is the responsibility of the application designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in acceptable operation. Refer to Figure 11-1 and Table 11-2 for VDD rise time and stability requirements for this mode of operation.
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PIC12F519
8.2
8.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 8-2:
EXTERNAL CLOCK INPUT OPERATION (XT OR LP OSC CONFIGURATION)
OSC1 PIC12F519
The PIC12F519 device can be operated in up to four different oscillator modes. The user can program using the Configuration bits (FOSC<1:0>), to select one of these modes: * * * * LP: XT: INTRC: EXTRC: Low-Power Crystal Crystal/Resonator Internal 4 MHz or 8 MHz Oscillator External Resistor/Capacitor
Clock from ext. system Open
OSC2
TABLE 8-1:
Osc Type XT Note:
8.2.2
CRYSTAL OSCILLATOR/CERAMIC RESONATORS
CAPACITOR SELECTION FOR CERAMIC RESONATORS
Cap. Range C1 30 pF Cap. Range C2 30 pF
In XT or LP modes, a crystal or ceramic resonator is connected to the (GP5)/OSC1/(CLKIN) and (GP4)/OSC2 pins to establish oscillation (Figure 8-1). The PIC12F519 oscillator designs require the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT or LP modes, the device can have an external clock source drive the (GP5)/OSC1/CLKIN pin (Figure 8-2). When the part is used in this fashion, the output drive levels on the OSC2 pin are very weak. This pin should be left open and unloaded. Also when using this mode, the external clock should observe the frequency limits for the clock mode chosen (XT or LP). Note 1: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required.
Resonator Freq. 4.0 MHz
Component values shown are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.
TABLE 8-2:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC12F519(2)
Cap.Range C1 15 pF 47-68 pF 15 pF 15 pF Cap. Range C2 15 pF 47-68 pF 15 pF 15 pF
Osc Type LP XT
Resonator Freq. 32 kHz(1) 200 kHz 1 MHz 4 MHz
Note 1:
FIGURE 8-1:
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (XT OR LP OSC CONFIGURATION)
OSC1 PIC12F519 Sleep RF(3) OSC2 To internal logic
2:
C1(1)
XTAL RS(2) C2(1) Note 1: 2: 3:
For VDD > 4.5V, C1 = C2 30 pF is recommended. Component values shown are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
See Capacitor Selection tables for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF approx. value = 10 M.
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PIC12F519
8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 8.2.4 EXTERNAL RC OSCILLATOR
Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 8-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. For timing insensitive applications, the RC circuit option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 8-5 shows how the R/C combination is connected to the PIC12F519 device. For REXT values below 3.0 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. It is recommended keeping REXT between 5.0 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), it is recommended using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See Figure 11-1 and Figure 11-2.
FIGURE 8-3:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices 4.7k 74AS04 74AS04 CLKIN PIC12F519 10k XTAL
+5V 10k
FIGURE 8-5:
VDD
EXTERNAL RC OSCILLATOR MODE
10k REXT 20 pF 20 pF OSC1 Internal clock
Figure 8-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
CEXT VSS
N PIC16F519
8.2.5 FIGURE 8-4: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
330 74AS04 0.1 mF XTAL PIC12F519 74AS04 CLKIN To Other Devices
INTERNAL 4/8 MHz RC OSCILLATOR
330 74AS04
The internal RC oscillator provides a fixed 4/8 MHz (nominal) system clock at VDD = 3.5V and 25C, (see Section 11.0 "Electrical Characteristics" for information on variation over voltage and temperature). In addition, a calibration instruction is programmed into the last address of memory, which contains the calibration value for the internal RC oscillator. This location is always non-code protected, regardless of the code-protect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the Reset vector. This will load the W register with the calibration value upon Reset and the
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PIC12F519
PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will "trim" the internal oscillator to remove process variation from the oscillator frequency. Note: Erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later.
8.3
Reset
The device differentiates between various kinds of Reset: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Time-out Reset during normal operation WDT Time-out Reset during Sleep Wake-up from Sleep on pin change
For the PIC12F519 device, only bits <7:1> of OSCCAL are used for calibration. See Register 4-3 for more information. Note: The bit 0 of the OSCCAL register is unimplemented and should be written as `0' when modifying OSCCAL for compatibility with future devices.
Some registers are not reset in any way, and they are unknown on Power-on Reset (POR) and unchanged in any other Reset. Most other registers are reset to "Reset state" on Power-on Reset (POR), MCLR, WDT or Wake-up on pin change Reset during normal operation. They are not affected by a WDT Reset during Sleep or MCLR Reset during Sleep, since these Resets are viewed as resumption of normal operation. The exceptions to this are TO, PD and GPWUF bits. They are set or cleared differently in different Reset situations. These bits are used in software to determine the nature of Reset. See Table 8-3 for a full description of Reset states of all registers.
TABLE 8-3:
Register W INDF TMR0 PCL STATUS FSR OSCCAL PORTB OPTION TRIS EECON EEDATA EEADR Legend: Note 1: 2: 3:
RESET CONDITIONS FOR REGISTERS
Address -- 00h 01h 02h 03h 04h 05h 06h -- -- 21h 25h 26h Power-on Reset qqqq qqq0(1) xxxx xxxx xxxx xxxx 1111 1111 0-01 1xxx 110x xxxx 1111 111--xx xxxx 1111 1111 --11 1111 ---0 x000 xxxx xxxx --xx xxxx MCLR Reset, WDT Time-out, Wake-up On Pin Change qqqq qqq0(1) uuuu uuuu uuuu uuuu 1111 1111 q-0q quuu(2), (3) 11uu uuuu uuuu uuu--uu uuuu 1111 1111 --11 1111 ---0 q000 uuuu uuuu --uu uuuu
u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. See Table 8-4 for Reset value for specific conditions. If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
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PIC12F519
TABLE 8-4:
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset during Sleep WDT Reset normal operation Wake-up from Sleep on pin change Legend: u = unchanged, x = unknown
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h 0-01 1xxx 0-0u uuuu 0-01 0uuu 0-00 0uuu 0-00 uuuu 1-01 0uuu
8.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the `1' state), enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD and the pin is assigned to be a I/O. See Figure 8-6.
FIGURE 8-6:
GPPU
MCLR SELECT
The Power-on Reset circuit and the Device Reset Timer (see Section 8.5 "Device Reset Timer (DRT)") circuit are closely related. On power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms or 1 ms, it will reset the Reset latch and thus end the on-chip Reset signal. A power-up example where MCLR is held low is shown in Figure 8-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT after MCLR goes high. In Figure 8-9, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be GP3). The VDD is stable before the Start-up timer times out and there is no problem in getting a proper Reset. However, Figure 8-10 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip may not function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 8-9). Note: When the devices start normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.
GP3/MCLR/VPP MCLRE Internal MCLR
8.4
Power-on Reset (POR)
The PIC12F519 device incorporates an on-chip Power-on Reset (POR) circuitry, which provides an internal chip Reset for most power-up situations. The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program the GP3/MCLR/VPP pin as MCLR and tie through a resistor to VDD, or program the pin as GP3, in which case, an internal weak pull-up resistor is implemented using a transistor (refer to Table 11-4 for the pull-up resistor ranges). This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Section 11.0 "Electrical Characteristics" for details. When the devices start normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the devices must be held in Reset until the operating parameters are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 8-7.
For additional information, refer to Application Note AN522, "Power-Up Considerations" (DS00522)
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PIC12F519
FIGURE 8-7:
VDD Power-up Detect POR (Power-on Reset)
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
GP3/MCLR/VPP MCLR Reset S Q
MCLRE WDT Time-out Pin Change Sleep WDT Reset Start-up Timer (10 s, 1 ms or 18 ms)
R
Q CHIP Reset
Wake-up on pin Change Reset
FIGURE 8-8:
VDD MCLR Internal POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
TDRT
DRT Time-out Internal Reset
FIGURE 8-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR Internal POR TDRT
DRT Time-out
Internal Reset
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PIC12F519
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1 VDD MCLR Internal POR TDRT
DRT Time-out
Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
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PIC12F519
8.5 Device Reset Timer (DRT) 8.6 Watchdog Timer (WDT)
On the PIC12F519 device, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 8-5). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the devices in a Reset condition after MCLR has reached a logic high (VIH MCLR) level. Programming GP3/MCLR/VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases. This allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the GP3/MCLR/VPP pin as a general purpose input. The Device Reset Time delays will vary from chip-to-chip due to VDD, temperature and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out from Sleep. This is particularly important for applications using the WDT to wake from Sleep mode automatically. Reset sources are POR, MCLR, WDT time-out and wake-up on pin change. See Section 8.8.2 "Wake-up from Sleep", Notes 1, 2 and 3. The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the external RC oscillator of the (GP5)/OSC1/CLKIN pin and the internal 4 or 8 MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration WDTE as a `0' (see Section 8.1 "Configuration Bits"). Refer to the PIC12F519 Programming Specification (DS41316) to determine how to access the Configuration Word.
8.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst-case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.
TABLE 8-5:
Oscillator Configuration
DRT (DEVICE RESET TIMER PERIOD)
POR Reset 1 ms (typical) 18 ms (typical) Subsequent Resets 10 s (typical) 18 ms (typical)
8.6.2
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device Reset. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT wake-up Reset.
INTOSC, EXTRC LP, XT
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PIC12F519
FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source (Figure 7-1) 0 Watchdog Time 1 M U X Postscaler
8-to-1 MUX WDT Enable Configuration Bit PSA
PS<2:0>
To Timer0 (Figure 7-3) 0 MUX 1 PSA
WDT Time-out
Note 1:
PSA, PS<2:0> are bits in the OPTION register.
TABLE 8-6:
Name OPTION Legend:
SUMMARY OF REGISTER ASSOCIATED WITH THE WATCHDOG TIMER
Bit 7 GPWU Bit 6 GPPU Bit 5 T0CS Bit 4 T0SE Bit 3 PSA Bit 2 PS2 Bit 1 PS1 Bit 0 PS0 Value on POR, BOR 1111 1111 Value on all other Resets 1111 1111
Shaded boxes = Not used by Watchdog Timer.
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PIC12F519
8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF)
8.8.2 WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 5. 6. 7. An external Reset input on GP3/MCLR/VPP pin, when configured as MCLR. A Watchdog Timer Time-out Reset (if WDT was enabled). A change on input pin GP0, GP1 and GP3 when wake-up on change is enabled.
The TO, PD and (GPWUF) bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset.
TABLE 8-7:
GPWUF 0 0 0 0 0 1 TO 0 0 1 1 u 1
TO/PD/(GPWUF) STATUS AFTER RESET
PD 0 u 0 1 u 0 Reset Caused By WDT wake-up from Sleep WDT time-out (not from Sleep) MCLR wake-up from Sleep Power-up MCLR not during Sleep Wake-up from Sleep on pin change
These events cause a device Reset. The TO, PD and GPWUF bits can be used to determine the cause of device Reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The GPWUF bit indicates a change in state while in Sleep at pins GP0, GP1 and GP3 (since the last file or bit operation on GPIO port). Note: Caution: Right before entering Sleep, read the input pins. When in Sleep, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode.
Legend: u = unchanged Note 1: The TO, PD and GPWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR input does not change the TO, PD and GPWUF Status bits.
The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source.
8.8
Power-down Mode (Sleep)
A device may be powered down (Sleep) and later powered up (wake-up from Sleep).
8.8.1
SLEEP
The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or high-impedance). Note: A Reset generated by a WDT time-out does not drive the MCLR pin low.
For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the GP3/MCLR/VPP pin must be at a logic high level if MCLR is enabled.
(c) 2008 Microchip Technology Inc.
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PIC12F519
8.9 Program Verification/Code Protection
FIGURE 8-12: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC12F519 VDD VSS MCLR/VPP GP1/ICSPCLK GP0/ICSPDAT VDD To Normal Connections
If the code protection bits have not been programmed, the on-chip program and data memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the setting of the program memory's code protection bit. If the code protect bit specific to the FLASH data memory is programmed, then none of the contents of this memory region can be verified externally.
External Connector Signals +5V 0V VPP CLK Data
8.10
ID Locations
Four memory locations are designated as ID locations where users can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations. The upper bits should be programmed as 0s.
8.11
In-Circuit Serial ProgrammingTM
The PIC12F519 device can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows users to manufacture boards with unprogrammed PIC12F519 device and then program the PIC12F519 device just before shipping the product. This also allows the most recent firmware, or a custom firmware, to be programmed. The PIC12F519 device is placed into a Program/Verify mode by holding the GP1 and GP0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). The GP1 pin becomes the programming clock, and the GP0 pin becomes the programming data. Both GP1 and GP0 pins are Schmitt Trigger inputs in this mode. After Reset, a 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a Load or a Read. For complete details of serial programming, please refer to the "PIC12F519 Memory Programming Specification," (DS41316). A typical In-Circuit Serial Programming connection is shown in Figure 8-12.
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PIC12F519
9.0 INSTRUCTION SET SUMMARY
The PIC12F519 instruction set is highly orthogonal and is comprised of three basic categories. * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC12F519 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 9-1, while the various opcode fields are summarized in Table 9-1. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator which selects the number of the bit affected by the operation, while `f' represents the number of the file in which the bit is located. For literal and control operations, `k' represents an 8 or 9-bit constant or literal value. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Figure 9-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where `h' signifies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR INSTRUCTIONS
6 5 d 4 f (FILE #) 0
Byte-oriented file register operations 11 OPCODE
d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 87 54 b (BIT #) 0 f (FILE #)
TABLE 9-1:
Field f W b k x
OPCODE FIELD DESCRIPTIONS
Description
b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 OPCODE k = 8-bit immediate value Literal and control operations - GOTO instruction 11 OPCODE k = 9-bit immediate value 9 8 k (literal) 0 8 7 k (literal) 0
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0 (store result in W) d = 1 (store result in file register `f') Default is d = 1 Label name Top-of-Stack Program Counter Watchdog Timer counter Time-out bit Power-down bit Destination, either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of User defined term (font is courier)
d
label TOS PC WDT TO PD dest [ ( <> italics ] )
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TABLE 9-2:
Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d
INSTRUCTION SET SUMMARY
12-Bit Opcode Description Cycles MSb LSb Status Notes Affected
0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decrement f 1 Z 2, 4 0010 11df ffff Decrement f, Skip if 0 1(2) None 2, 4 1 0010 10df ffff Increment f Z 2, 4 1(2) 0011 11df ffff Increment f, Skip if 0 None 2, 4 1 0001 00df ffff Inclusive OR W with f Z 2, 4 1 0010 00df ffff Move f Z 2, 4 1 0000 001f ffff Move W to f None 1, 4 1 0000 0000 0000 No Operation None 1 0011 01df ffff Rotate left f through Carry C 2, 4 1 0011 00df ffff Rotate right f through Carry C 2, 4 1 0000 10df ffff C, DC, Z 1, 2, 4 Subtract W from f 1 0011 10df ffff Swap f None 2, 4 1 0001 10df ffff Exclusive OR W with f Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS 0100 bbbf ffff None 2, 4 1 Bit Clear f BCF f, b 0101 bbbf ffff None 2, 4 1 Bit Set f BSF f, b 0110 bbbf ffff None Bit Test f, Skip if Clear 1(2) BTFSC f, b 1(2) 0111 bbbf ffff None f, b Bit Test f, Skip if Set BTFSS LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL 1 k Call Subroutine 2 1001 kkkk kkkk None CLRWDT - Clear Watchdog Timer 1 0000 0000 0100 TO, PD None GOTO k Unconditional branch 2 101k kkkk kkkk Z IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk None MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION - Load OPTION register 1 0000 0000 0010 None RETLW k Return, place literal in W 2 1000 kkkk kkkk SLEEP - Go into Standby mode 1 0000 0000 0011 TO, PD None 3 TRISGPIO f Load TRISGPIO register 1 0000 0000 0fff Z XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Note 1: The 9th bit of the program counter will be forced to a `0' by any instruction that writes to the PC except for GOTO. See Section 4.6 "Program Counter". 2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of GPIO. A `1' forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).
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ADDWF Syntax: Operands: Operation: Description: Add W and f [ label ] ADDWF 0 f 31 d [0,1] (W) + (f) (dest) Add the contents of the W register and register `f'. If `d' is'0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d BCF Syntax: Operands: Operation: Status Affected: Description: Bit Clear f [ label ] BCF 0 f 31 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
Status Affected: C, DC, Z
ANDLW Syntax: Operands: Operation: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W).AND. (k) (W) k
BSF Syntax: Operands: Operation: Status Affected:
Bit Set f [ label ] BSF 0 f 31 0b7 1 (f) None f,b
Status Affected: Z The contents of the W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register.
Description: Bit `b' in register `f' is set.
ANDWF Syntax: Operands: Operation: Description:
AND W with f [ label ] ANDWF 0 f 31 d [0,1] (W) .AND. (f) (dest) The contents of the W register are AND'ed with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 31 0b7 skip if (f) = 0 None If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.
Status Affected: Z
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 31 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRW Syntax: Operands: Operation: Clear W [ label ] CLRW None 00h (W); 1Z Z The W register is cleared. Zero bit (Z) is set.
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k 0 k 255 (PC) + 1 Top-of-Stack; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8> None Subroutine call. First, return address (PC + 1) is pushed onto the stack. The eight-bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two-cycle instruction.
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD TO, PD The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 31 00h (f); 1Z Z The contents of register `f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 31 d [0,1] (f) (dest) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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DECF Syntax: Operands: Operation: Status Affected: Description: Decrement f [ label ] DECF f,d 0 f 31 d [0,1] (f) - 1 (dest) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. INCF Syntax: Operands: Operation: Status Affected: Description: Increment f [ label ] 0 f 31 d [0,1] (f) + 1 (dest) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. INCF f,d
DECFSZ Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 31 d [0,1] (f) - 1 d; None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. skip if result = 0
INCFSZ Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0 [ label ] 0 f 31 d [0,1] (f) + 1 (dest), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `0', then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. INCFSZ f,d
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 511 k PC<8:0>; STATUS<6:5> PC<10:9> None GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
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IORWF Syntax: Operands: Operation: Status Affected: Description: Inclusive OR W with f [ label ] 0 f 31 d [0,1] (W).OR. (f) (dest) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. IORWF f,d MOVWF Syntax: Operands: Operation: Status Affected: Description: Move W to f [ label ] 0 f 31 (W) (f) None Move data from the W register to register `f'. MOVWF f
MOVF Syntax: Operands: Operation: Status Affected: Description:
Move f [ label ] 0 f 31 d [0,1] (f) (dest) Z The contents of register `f' are moved to destination `d'. If `d' is `0', destination is the W register. If `d' is `1', the destination is file register `f'. `d' = 1 is useful as a test of a file register, since status flag Z is affected. MOVF f,d
NOP Syntax: Operands: Operation: Status Affected: Description:
No Operation [ label ] None No operation None No operation. NOP
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into the W register. The "don't cares" will assembled as `0's. MOVLW k 0 k 255
OPTION Syntax: Operands: Operation: Status Affected: Description:
Load OPTION Register [ label ] None (W) Option None The content of the W register is loaded into the OPTION register. Option
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RETLW Syntax: Operands: Operation: Status Affected: Description: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Status Affected: Description: SLEEP Syntax: Operands: Operation: Enter SLEEP Mode [label ] None 00h WDT; 0 WDT prescaler; 1 TO; 0 PD TO, PD, GPWUF Time-out Status bit (TO) is set. The Power-down Status bit (PD) is cleared. GPWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section 8.8 "Power-down Mode (Sleep)" on Sleep for more details. Subtract W from f [label ] SUBWF f,d 0 f 31 d [0,1] (f) - (W) (dest) C, DC, Z Subtract (two's complement method) the W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. SLEEP
RLF Syntax: Operands: Operation: Status Affected: Description:
Rotate Left f through Carry [ label ] 0 f 31 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C
register `f'
SUBWF Syntax: Operands: Operation: Status Affected: Description:
RLF
f,d
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] 0 f 31 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C
register `f'
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 31 d [0,1] (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W register. If `d' is `1', the result is placed in register `f'.
RRF f,d
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TRIS Syntax: Operands: Operation: Status Affected: Description: Load TRIS Register [ label ] TRIS f=6 (W) TRIS register f None TRIS register `f' (f = 6 or 7) is loaded with the contents of the W register. Operation: Status Affected: Description: f XORWF Syntax: Operands: Exclusive OR W with f [ label ] XORWF 0 f 31 d [0,1] (W) .XOR. (f) (dest) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR literal with W [label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
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10.0 DEVELOPMENT SUPPORT
10.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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10.2 MPASM Assembler 10.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
10.6 10.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
10.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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10.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 10.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
10.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
10.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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10.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
10.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
10.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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11.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
Ambient temperature under bias.......................................................................................................... -40C to +125C Storage temperature ............................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................... 0 to +6.5V Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) .................................................................................................................................. 700 mW Max. current out of VSS pin ................................................................................................................................ 200 mA Max. current into VDD pin ................................................................................................................................... 150 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................20 mA Max. output current sunk by any I/O pin .............................................................................................................. 25 mA Max. output current sourced by any I/O pin ......................................................................................................... 25 mA Max. output current sourced by I/O port .............................................................................................................. 75 mA Max. output current sunk by I/O port ................................................................................................................... 75 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL)
NOTICE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 11-1:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 8 Frequency (MHz) 10 20 25 INTOSC ONLY
PIC12F519 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
FIGURE 11-2:
MAXIMUM OSCILLATOR FREQUENCY TABLE
LP Oscillator Mode XT EXTRC INTOSC 0 200 kHz Frequency (MHz) 4 MHz 8 MHz
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11.1 DC Characteristics
DC CHARACTERISTICS: PIC12F519 (INDUSTRIAL)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) Min. 2.0
(2)
TABLE 11-1:
DC CHARACTERISTICS Param Sym. No. D001 D002 D003 D004 D005 D010 VDD VDR VPOR SVDD IDDP IDD Characteristic Supply Voltage RAM Data Retention Voltage VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current During Prog/ Erase. Supply Current(3,4)
Typ(1) Max. 5.5 1.5* Vss -- 250* 175 400 250 0.75 11 38 0.1 0.35 1.0 7.0 -- -- -- -- 250 700 400 1.2 20 54 1.2 2.2 3.0 16.0
Units V V V V/ms A A A A mA A A A A A A
Conditions See Figure 11-1 Device in Sleep mode See Section 8.4 "Power-on Reset (POR)" for details See Section 8.4 "Power-on Reset (POR)" for details
-- -- 0.05* -- -- -- -- -- -- --
FOSC = 4 MHz, VDD = 2.0V FOSC = 4 MHz, VDD = 5.0V FOSC = 8 MHz, VDD = 2.0V FOSC = 8 MHz, VDD = 5.0V FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V
D020 D022 * Note 1: 2: 3:
IPD IWDT
Power-down Current(5) WDT Current
-- -- -- --
4:
5:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail for external clock modes; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
(c) 2008 Microchip Technology Inc.
DS41319B-page 63
PIC12F519
TABLE 11-2: DC CHARACTERISTICS: PIC12F519 (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) Min. 2.0
(2)
DC CHARACTERISTICS Param Sym. No. D001 D002 D003 D004 D005 D010 VDD VDR VPOR SVDD IDDP IDD Characteristic Supply Voltage RAM Data Retention Voltage VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current During Prog/ Erase. Supply Current(3,4)
Typ(1) Max. 5.5 1.5* Vss -- 250* 175 400 250 0.75 11 38 0.1 0.35 1.0 7.0 -- -- -- -- 250 700 400 1.2 24 110 9.0 15.0 18 22
Units V V V V/ms A A mA A mA A A A A A A
Conditions See Figure 11-1 Device in Sleep mode See Section 8.4 "Power-on Reset (POR)" for details See Section 8.4 "Power-on Reset (POR)" for details
-- -- 0.05* -- -- -- -- -- -- --
FOSC = 4 MHz, VDD = 2.0V FOSC = 4 MHz, VDD = 5.0V FOSC = 8 MHz, VDD = 2.0V FOSC = 8 MHz, VDD = 5.0V FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 5.0V VDD = 2.0V VDD = 5.0V VDD = 2.0V VDD = 5.0V
D020 D022 * Note 1: 2: 3:
IPD IWDT
Power-down Current(5) WDT Current
-- -- -- --
4:
5:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail for external clock modes; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
DS41319B-page 64
(c) 2008 Microchip Technology Inc.
PIC12F519
TABLE 11-3:
DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified) Operating temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating voltage VDD range as described in DC specification. Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, T0CKI OSC1 (EXTRC mode) OSC1 (XT and LP modes) Vss Vss Vss Vss Vss Vss -- -- -- -- -- -- -- 2.0 0.25 VDD + 0.8V with Schmitt Trigger buffer MCLR, T0CKI OSC1 (EXTRC mode) OSC1 (XT and LP modes) 0.85 VDD 0.85 VDD 0.85 VDD 1.6 50 -- -- -- -- -- Output High Voltage I/O ports(3) VDD - 0.7 VDD - 0.7 Capacitive Loading Specs on Output Pins All I/O pins Flash Data Memory -- 100K 10K VMIN -- -- -- -- -- -- 250 -- 0.7 -- -- -- -- -- -- 1M 100K -- VDD VDD VDD VDD VDD VDD 400 1 5 5 0.6 0.6 -- -- 50 -- -- 5.5 V V V V V V A A A A V V V V pF E/W E/W V -40C TA +85C +85C TA +125C VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD, XT and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C (Note 1) 4.5 VDD 5.5V Otherwise For entire VDD range 0.8 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 V V V V V V (Note 1) For all 4.5 VDD 5.5V Otherwise Min. Typ Max. Units Conditions
DC CHARACTERISTICS
Param No.
Sym. VIL
D030 D030A D031 D032 D033 D033A VIH D040 D040A D041 D042 D042A D043 D070 D060 D061 D063 D080 D080A D090 D090A D101 D120 D120A D121 Note ED ED 1: 2: 3: 4: 5: IPUR IIL
Input High Voltage I/O ports with TTL buffer
I/O PORT weak pull-up current(5) Input Leakage Current(2), (3) I/O ports GP3/MCLR(4) OSC1 Output Low Voltage I/O ports
Byte endurance Byte endurance
VDRW VDD for read/write
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F519 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. This specification applies to GP3/MCLR configured as GP3 with internal pull-up disabled. This specification applies to all weak pull-up devices, including the weak pull-up found on GP3/MCLR. The current value listed will be the same whether or not the pin is configured as GP3 with pull-up enabled or MCLR.
(c) 2008 Microchip Technology Inc.
DS41319B-page 65
PIC12F519
TABLE 11-4:
VDD (Volts) GP0/GP1 2.0
PULL-UP RESISTOR RANGES
Temperature (C) -40 25 85 125 -40 25 85 125 -40 25 85 125 -40 25 85 125 Min. Typ. Max. Units
5.5
73K 73K 82K 86K 15K 15K 19K 23K 63K 77K 82K 86K 16K 16K 24K 26K
105K 113K 123K 132K 21K 22K 26K 29K 81K 93K 96K 100K 20K 21K 25K 27K
186K 187K 190K 190K 33K 34K 35K 35K 96K 116K 116K 119K 22K 23K 28K 29K

GP3 2.0
5.5
DS41319B-page 66
(c) 2008 Microchip Technology Inc.
PIC12F519
11.2 Timing Parameter Symbology and Load Conditions - PIC12F519
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase subscripts (pp) and their meanings: pp 2 ck cy drt io S F H I L Fall High Invalid (high-impedance) Low P R V Z Period Rise Valid High-impedance to CLKOUT Cycle time Device Reset Timer I/O port mc osc os t0 wdt MCLR Oscillator OSC1 T0CKI Watchdog Timer
T Time
Uppercase letters and their meanings:
FIGURE 11-3:
LOAD CONDITIONS - PIC12F519
Legend: pin CL VSS CL = 50 pF for all pins except OSC2 15 pF for OSC2 in XT or LP modes when external clock is used to drive OSC1
FIGURE 11-4:
EXTERNAL CLOCK TIMING - PIC12F519
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 3 3 4 4
(c) 2008 Microchip Technology Inc.
DS41319B-page 67
PIC12F519
11.3 AC Characteristics
EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 11.0 "Electrical Characteristics" Min. DC DC Oscillator Frequency
(2)
TABLE 11-5:
AC CHARACTERISTICS
Param No. 1A
Sym. FOSC
Characteristic External CLKIN Frequency(2)
Typ(1) -- -- -- -- -- -- -- -- -- -- 4/FOSC -- -- -- --
Max. 4 200 4 4 200 -- -- -- 10,000 -- DC -- -- 25* 50*
Units
Conditions
MHz XT Oscillator mode kHz LP Oscillator mode MHz EXTRC Oscillator mode MHz XT Oscillator mode kHz ns s ns ns s ns ns s ns ns XT Oscillator LP Oscillator XT Oscillator LP Oscillator LP Oscillator mode XT Oscillator mode LP Oscillator mode EXTRC Oscillator mode XT Oscillator mode LP Oscillator mode
DC 0.1 DC
1
TOSC
External CLKIN Period(2) Oscillator Period(2)
250 5 250 250 5
2 3 4 * Note 1: 2:
TCY TosL, TosH TosR, TosF
Instruction Cycle Time Clock in (OSC1) Low or High Time Clock in (OSC1) Rise or Fall Time
200 50* 2* -- --
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
DS41319B-page 68
(c) 2008 Microchip Technology Inc.
PIC12F519
TABLE 11-6: CALIBRATED INTERNAL RC FREQUENCIES
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1 Freq. Min. Tolerance 1% 2% 5% 7.92 7.84 7.60 Typ 8.00 8.00 8.00 Max. 8.08 8.16 8.40 Units Conditions
AC CHARACTERISTICS
Param No. F10
Sym. FOSC
Characteristic Internal Calibrated INTOSC Frequency(1)
MHz 3.5V, 25C MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.)
* These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
FIGURE 11-5:
I/O TIMING
Q4 Q1 Q2 Q3
OSC1
I/O Pin (input) 17 I/O Pin (output) Old Value 20, 21 19 18 New Value
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
(c) 2008 Microchip Technology Inc.
DS41319B-page 69
PIC12F519
TABLE 11-7: TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) AC CHARACTERISTICS -40C TA +125C (extended) Operating Voltage VDD range is described in Param No. 17 18 19 20 21 Sym. TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF Characteristic OSC1 (Q1 cycle) to Port Out Valid(2), (3) OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time)(2) Port Input Valid to OSC1 (I/O in setup time) Port Output Rise Time(3) Port Output Fall Time
(3)
Min. -- 50 20 -- --
Typ(1) -- -- -- 10 10
Max. 100* -- -- 50** 50**
Units ns ns ns ns ns
TBD = To be determined. * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 11-3 for loading conditions.
FIGURE 11-6:
VDD MCLR
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
30 Internal POR 32 DRT Time-out(2) Internal Reset Watchdog Timer Reset 31 34 I/O pin(1) 34 32
32
Note 1: 2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. Runs in MCLR or WDT Reset only in XT and LP.
DS41319B-page 70
(c) 2008 Microchip Technology Inc.
PIC12F519
TABLE 11-8: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER - PIC12F519
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section TABLE 11-3: "DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)" Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no prescaler) Device Reset Timer Period Standard Short 34 * Note 1: TIOZ I/O High-impedance from MCLR low 9* 9* 0.5* 0.5* -- 18* 18* 1.125* 1.125* -- 30* 40* 2* 2.5* 2000* ms ms ms ms ns VDD = 5.0V (Industrial) VDD = 5.0V (Extended) VDD = 5.0V (Industrial) VDD = 5.0V (Extended) Min. 2000* 9* 9* Typ(1) -- 18* 18* Max. -- 30* 40* Units ns ms ms Conditions VDD = 5.0V VDD = 5.0V (Industrial) VDD = 5.0V (Extended)
AC CHARACTERISTICS
Param No. 30 31 32
Sym. TMCL TWDT TDRT
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 11-9:
DRT (DEVICE RESET TIMER PERIOD)
POR Reset 1 ms (typical) 18 ms (typical) Subsequent Resets 10 s (typical) 18 ms (typical)
Oscillator Configuration IntRC and ExtRC XT and LP
FIGURE 11-7:
TIMER0 CLOCK TIMINGS
T0CKI 40 42 41
(c) 2008 Microchip Technology Inc.
DS41319B-page 71
PIC12F519
TABLE 11-10: TIMER0 CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section TABLE 11-3: "DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)" Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N Typ(1) Max. Units -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns Conditions
AC CHARACTERISTICS
Param Sym. No. 40 41 42 Tt0H Tt0L Tt0P
Whichever is greater. N = Prescale Value (1, 2, 4,..., 256)
* Note 1:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 11-11: FLASH DATA MEMORY WRITE/ERASE REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Operating Voltage VDD range is described in Section TABLE 11-3: "DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)" Min. Typ(1) Max. Units Conditions
AC CHARACTERISTICS
Param Sym. No. 43 TDW
Characteristic
Flash Data Memory 2 3.5 5 ms Write Cycle Time Flash Data Memory 2 3 4 ms 44 TDE Erase Cycle Time * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41319B-page 72
(c) 2008 Microchip Technology Inc.
PIC12F519
12.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range.
FIGURE 12-1:
800 700 600 500
TYPICAL IDD vs. FOSC OVER VDD (XT, EXTRC mode)
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
IDD (A)
5V
400 300 200 100 0 0 1 2 3 4 5
2V
FOSC (MHz)
FIGURE 12-2:
800 700 600 500
MAXIMUM IDD vs. FOSC OVER VDD (XT, EXTRC mode)
5V
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
IDD (A)
400 300
2V
200 100 0 0 1 2 3 4 5
FOSC (MHz)
(c) 2008 Microchip Technology Inc.
DS41319B-page 73
PIC12F519
FIGURE 12-3:
120
IDD vs. VDD OVER FOSC (LP MODE)
Typical: Statistical Mean @25C Industrial: Mean (Worst-Case Temp) + 3 (-40C to 85C)
100
Extended: Mean (Worst-Case Temp) + 3 (-40C to 125C)
32 kHz Maximum Extended
80
IDD (A)
60
32 kHz Maximum Industrial
40
32 kHz Typical
20
0 1 2 3 4 5 6
VDD (V)
DS41319B-page 74
(c) 2008 Microchip Technology Inc.
PIC12F519
FIGURE 12-4:
0.45 0.40 0.35 0.30 IPD (A) 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 12-5:
18.0 16.0 14.0
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. 125C
12.0 IPD (A) 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C
(c) 2008 Microchip Technology Inc.
DS41319B-page 75
PIC12F519
FIGURE 12-6:
9 8 7 6 IPD (A) 5 4 3 2 1 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
TYPICAL WDT IPD vs. VDD
FIGURE 12-7:
25.0
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
20.0
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. 125C
IPD (A)
15.0
10.0
5.0
Max. 85C
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41319B-page 76
(c) 2008 Microchip Technology Inc.
PIC12F519
FIGURE 12-8:
50 45 40 Max. 85C 35 30 Time (ms) Typical. 25C 25 20 Min. -40C 15 10 5 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 125C Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)
FIGURE 12-9:
0.8
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
0.7
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
Max. 125C
0.6
0.5 VOL (V)
Max. 85C
0.4 Typical 25C
0.3
0.2 Min. -40C 0.1
0.0 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
(c) 2008 Microchip Technology Inc.
DS41319B-page 77
PIC12F519
FIGURE 12-10:
0.45 0.40 0.35 Max. 85C 0.30 0.25 Typ. 25C 0.20 0.15 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0 Typical: Statistical Mean @25C Typical: Statistical Mean Temp) + Maximum: Mean (Worst-Case @25xC 3 Maximum: Meas + 3 to 125xC) (-40xC (-40C to 125C)
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
Max. 125C
VOL (V)
Min. -40C
FIGURE 12-11:
3.5
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.0
Max. -40C Typ. 25C
2.5
Min. 125C 2.0 VOH (V)
1.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
1.0
0.5
0.0 0.0 -0.5 -1.0 -1.5 -2.0 IOH (mA) -2.5 -3.0 -3.5 -4.0
DS41319B-page 78
(c) 2008 Microchip Technology Inc.
PIC12F519
FIGURE 12-12:
5.5
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
5.0 Max. -40C
Typ. 25C 4.5 VOH (V) Min. 125C
4.0
3.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 IOH (mA) -3.0 -3.5 -4.0 -4.5 -5.0
FIGURE 12-13:
1.7
TTL INPUT THRESHOLD VIN vs. VDD
1.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C) Max. -40C
1.3 VIN (V)
Typ. 25C 1.1 Min. 125C 0.9
0.7
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2008 Microchip Technology Inc.
DS41319B-page 79
PIC12F519
FIGURE 12-14:
4.0 VIH Max. 125C 3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-Case Temp) + 3 (-40C to 125C)
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
VIH Min. -40C
3.0
VIN (V)
2.5
2.0 VIL Max. -40C 1.5 VIL Min. 125C
1.0
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 12-15:
45 40 35 30 DRT (ms) 25 20 15 10 5 0 2.0
DEVICE RESET TIMER (XT AND LP) vs. VDD
Max. 125C
Max. 85C Typical 25C Min. -40C
2.5
3.0
3.5 VDD (V)
4.0
4.5
5.0
5.5
DS41319B-page 80
(c) 2008 Microchip Technology Inc.
PIC12F519
13.0
13.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP XXXXXXXX XXXXXNNN YYWW Example 12F519-I /P017 0610
8-Lead SOIC (3.90 mm) XXXXXXXX XXXXYYWW NNN
Example 12F519-I /SN0610 017
8-Lead MSOP
Example
XXXXXX YWWNNN
519/MS 610017
8-Lead 2x3 DFN*
Example
XXX YWW NN
BY0 610 17
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PIC(R) device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 2008 Microchip Technology Inc.
DS41319B-page 81
PIC12F519
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(c) 2008 Microchip Technology Inc.
DS41319B-page 87
PIC12F519
APPENDIX A: REVISION HISTORY
Revision A (May 2007) Original release of this document. Revision B (September 2008) Added DC and AC Characteristics graphs; Updated Electrical Characteristics section; Updated Package Drawings and made general edits.
DS41319B-page 88
(c) 2008 Microchip Technology Inc.
PIC12F519
INDEX
A
ALU ....................................................................................... 9 Assembler MPASM Assembler..................................................... 58
M
Memory Map PIC12F519 ................................................................. 13 Memory Organization ......................................................... 13 Data EEPROM Memory ............................................. 21 Program Memory (PIC12F519) .................................. 13 Microchip Internet Web Site................................................ 91 MPLAB ASM30 Assembler, Linker, Librarian ..................... 58 MPLAB ICD 2 In-Circuit Debugger ..................................... 59 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator...................................................... 59 MPLAB Integrated Development Environment Software.... 57 MPLAB PM3 Device Programmer ...................................... 59 MPLAB REAL ICE In-Circuit Emulator System .................. 59 MPLINK Object Linker/MPLIB Object Librarian .................. 58
B
Block Diagram On-Chip Reset Circuit ................................................. 43 Timer0......................................................................... 31 TMR0/WDT Prescaler................................................. 35 Watchdog Timer.......................................................... 46
C
C Compilers MPLAB C18 ................................................................ 58 MPLAB C30 ................................................................ 58 Carry ..................................................................................... 9 Clocking Scheme ................................................................ 12 Code Protection ............................................................ 37, 48 CONFIG1 Register.............................................................. 38 Configuration Bits................................................................ 37 Customer Change Notification Service ............................... 91 Customer Notification Service............................................. 91 Customer Support ............................................................... 91
O
OPTION Register................................................................ 17 OSC selection..................................................................... 37 OSCCAL Register............................................................... 18 Oscillator Configurations..................................................... 39 Oscillator Types HS............................................................................... 39 LP ............................................................................... 39 RC .............................................................................. 39 XT ............................................................................... 39
D
DC and AC Characteristics ................................................. 73 Graphs and Tables ..................................................... 73 Development Support ......................................................... 57 Digit Carry ............................................................................. 9
P
PIC12F519 Device Varieties................................................. 7 PICSTART Plus Development Programmer....................... 60 POR Device Reset Timer (DRT) ................................... 37, 45 PD............................................................................... 47 TO............................................................................... 47 Power-down Mode.............................................................. 47 Prescaler ............................................................................ 34 Program Counter ................................................................ 19
E
Errata .................................................................................... 3
F
FSR ..................................................................................... 20 FSR Register ...................................................................... 20 Fuses. See Configuration Bits
G
GPIO ................................................................................... 23
Q
Q cycles .............................................................................. 12
I
I/O Interfacing ..................................................................... 25 I/O Port................................................................................ 23 I/O Ports .............................................................................. 23 I/O Programming Considerations........................................ 30 ID Locations .................................................................. 37, 48 INDF.................................................................................... 20 INDF Register ..................................................................... 20 Indirect Data Addressing..................................................... 20 Instruction Cycle ................................................................. 12 Instruction Flow/Pipelining .................................................. 12 Instruction Set Summary..................................................... 50 Internet Address.................................................................. 91
R
RC Oscillator....................................................................... 40 Reader Response............................................................... 92 Read-Modify-Write.............................................................. 30 Register File Map PIC16C57/CR57......................................................... 14 Registers CONFIG1 (Configuration Word Register 1)................ 38 Special Function ......................................................... 14 Reset .................................................................................. 37
S
Sleep ............................................................................ 37, 47 Software Simulator (MPLAB SIM) ...................................... 58 Special Features of the CPU .............................................. 37 Special Function Registers ................................................. 14 Stack................................................................................... 19 STATUS Register ........................................................... 9, 16
L
Loading of PC ..................................................................... 19
(c) 2008 Microchip Technology Inc.
DS41319B-page 89
PIC12F519
T
Timer0 Timer0 (TMR0) Module ............................................... 31 TMR0 with External Clock........................................... 33 Timing Diagrams and Specifications................................... 67 Timing Parameter Symbology and Load Conditions........... 67 TRIS Registers.................................................................... 23
W
Wake-up from Sleep ........................................................... 47 Watchdog Timer (WDT) ................................................ 37, 45 Period.......................................................................... 45 Programming Considerations ..................................... 45 WWW Address.................................................................... 91 WWW, On-Line Support........................................................ 3
Z
Zero bit .................................................................................. 9
DS41319B-page 90
(c) 2008 Microchip Technology Inc.
PIC12F519
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2008 Microchip Technology Inc.
DS41319B-page 91
PIC12F519
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC12F519 Questions: 1. What are the best features of this document? Y N Literature Number: DS41319B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41319B-page 92
(c) 2008 Microchip Technology Inc.
PIC12F519
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC12F519 PIC12F519T (Tape and Reel) I E MC MS P SN = = = = = = -40C to +85C (Industrial) -40C to +125C (Extended) 8L DFN 2x3 (DUAL Flatpack No-Leads) MSOP (Pb-free) 300 mil PDIP (Pb-free) 3.90 mm SOIC, 8-LD (Pb-free) c) PIC12F519-I/P = Industrial temp., PDIP package (Pb-free) PIC12F519T-I/SN = Tape and Reel, Industrial temp., SOIC package PIC12F519 - E/MS 303 = Extended temp., MSOP package, QTP pattern #303
Temperature Range:
Package:
Pattern: Note:
Special Requirements Tape and Reel available for only the following packages: SOIC, DFN and MSOP.
(c) 2008 Microchip Technology Inc.
DS41319B-page 93
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/02/08
DS41319B-page 94
(c) 2008 Microchip Technology Inc.

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